1. Technical Field
This invention relates generally to digital signal processing, and more particularly, a scalable multiplier configured to optimize the amount of memory utilized when performing multiplication in a computing device.
2. Description of the Related Art
In analog and digital computing the need often arises for a circuit that accepts two inputs, a multiplicand and a multiplier, and produces an output proportional to their product. Such a circuit, often referred to as a multiplier, is a basic building block used in numeric processing units such as digital signal processors. Utilizing AND gates and full adders, multiplication can be implemented in much the same way as hand multiplication. First, each digit of the multiplier can be multiplied by the multiplicand to generate partial products, the partial products for each successive digit being shifted one digit left. Each of the shifted partial products then can be summed to generate the product. Such an implementation has been referred to as Braun's multiplier and is considered by many to be a “brute force” method of performing multiplication.
Multiplication of two values, X and Y, can also be expressed asX*Y=([X+Y]/2)2−([X−Y]/2)2This expanded multiplication method commonly is used in implementing analog multipliers because this multiplication method reduces the multiplication process to merely producing the difference of two squared numbers. Like the Braun method, however, the expanded multiplication method can be processor and memory intensive, especially when both the multiplicand and multiplier are large values. In fact, a typical multiplier which has implemented expanded multiplication must process 2×216 combinations of multipliers and multiplicands when calculating the product of 16 bit analog values, hence requiring a correspondingly large amount of memory allocation and power.
Notably, the implementation and use of the expanded multiplication method can be especially taxing on digital signal processing (DSP) systems that must perform a large number of multiplications repeatedly, such as in video editing and audio processing. Specifically, the use of the expanded multiplication method in a DSP tends to require a large amount of DSP memory resources and can consume much power. Thus, the implementation of the expanded multiplication method in a DSP is not practical where the DSP has been included as part of a system in a portable device.
Importantly, the use of the expanded multiplication method can result in undesirable power dissipation. For many applications, speed and performance factors associated with a multiplication circuit can outweigh power dissipation inasmuch as many computing devices have access to an adequate power supply. Still, in battery powered devices, the power dissipation factor can become more important. In particular, in communications devices like cellular telephones in which battery life can be both an important marketing and operational element, it would be preferable to include a multiplication circuit which consumes less power, even at the expense of performance.